1. Field of the Invention
The present invention relates to the field of networking. More specifically, a first aspect of the present invention relates to packet diversion and insertion for high-speed network trafficking equipment, such as 10-gigabit optical-electrical routers or switches. A second aspect of the present invention relates to packet buffering and flushing of the buffered packets. The present invention also relates to addressing both aspects in support of multiple datacom and telecom protocols.
2. Background Information
With advances in integrated circuit, microprocessor, networking and communication technologies, increasing number of devices, in particular, digital computing devices, are being networked together. Devices are often first coupled to a local area network, such as an Ethernet based office/home network. In turn, the local area networks are interconnected together through wide area networks, such as SONET networks, ATM networks, Frame Relay, and the like. Of particular importance is the TCP/IP based global inter-network, the Internet.
As a result of this trend of increased connectivity, increasing number of applications that are network dependent are being deployed. Examples of these network dependent applications include but are not limited to, the World Wide Web, e-mail, Internet based telephony, and various types of e-commerce and enterprise applications. The success of many content/service providers as well as commerce sites depend on high-speed delivery of a large volume of data across wide areas. In turn, the trend leads to increased demand for high-speed data trafficking.
Historically, data communication protocols specified the requirements of local/regional area networks, whereas telecommunication protocols specified the requirements of the regional/wide area networks. The rapid growth of high volume, high-speed data routing over the Internet has fueled a convergence of data communication (datacom) and telecommunication (telecom) protocols and requirements. It is increasingly important that data traffic be carried efficiently at high speed across local, regional and wide area networks.
When routing or switching network traffic, a need often arises to divert some of the packets being routed/switched onto a routing path (to perform additional processing or dropping the packets), or insert additional packets into the packet streams being received off a routing path. FIG. 1 illustrates a typical prior art approach to providing such functionality of packet diversion and/or packet insertion to an “intermediate” networking equipment. Illustrated is an example networking switch/router 50 having switching/routing fabric 52, including a number of ingress/egress points 54a-54n, through which packets may be received and/or routed onto the corresponding coupled mediums (routing paths). To provide the desired packet diversion and/or insertion functionality, one or more of ingress/egress points 54a-54n, such as point 54n, are reserved for the coupling of one or more companion processors 56 (also referred to as host processors), as opposed to the mediums connecting the switch/router to a network. The basic implementations of these switches/routers would route all packets through host processors 56, to enable host processors 56 to selectively divert some of the packets from the various routing paths (for additional processing or dropping the packets) or to selectively inject additional packets into the packet streams of the various routing paths. In other more advanced implementations, additional switching/routing resources (such as programmable switching/routing tables) (not shown) may be employed to facilitate routing of some of the packets of the routing paths to host processors 56 for “processing” (“diversion”), and routing of the packets injected by host processors 56 onto the routing paths of their selection (“insertion”).
These prior art approaches all suffer from the common disadvantage in that at least one of the ingress/egress point of switching/routing fabric 52 is used for the coupling of a host processor 56. As networking speed increases, with more and more packets being routed/switched over a unit of time, host processor 56 becomes a bottleneck under these prior art approaches. Typically, more than one host processor 56 have to be employed, resulting in more than one ingress/egress points 54a-54n being consumed, which in turn leads to a reduction in the bandwidth of networking equipment 50 (for a given amount of switching/routing resources (fabric 52)). Increasingly, these architectures are becoming un-scalable for the type of efficient, high speed (10 Gb and beyond) networking that spans local, regional, and wide area networks, especially when multiple datacom and telecom protocols are involved.
Thus, an improved approach to packet diversion and insertion, including buffering and flushing of buffered packets, is desired.